(1) Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an improvement of a semiconductor memory device using one-transistor one-capacitor type memory cells.
(2) Description of the Related Art
A semiconductor memory device constructed by one-transistor one-capacitor type memory cells is well known and is described in, for example, Japanese Patent Publication No. 56-6072 published in Japan on Feb. 9, 1981.
In a one-transistor one-capacitor type semiconductor memory device, each memory cell is connected between a word line and one of a pair of bit lines. The memory cell is constructed by one transistor functioning as a transfer gate and one capacitor for storing data.
Accompanying the increase in integration density, the width of the word line, usually formed by aluminum having a small resistivity, has become narrower, resulting in a large wiring resistance, and if the word line is formed by the polysilicon, which has a larger resistivity than aluminum, the wiring resistance will become even larger. Further, the wiring resistance is not constant in all semiconductor memory devices but varies depending on the manufacturing processes of the devices.
Each word line is driven by a word decoder, and a number of memory cells are connected to the word line. By driving the word line, charges stored in each memory cell connected to the word line flow out on the corresponding bit line. A sense amplifier is then activated to amplify the potential difference between a pair of bit lines.
Because of the wiring resistance of the word line as mentioned above, the timing at which the sense amplifier is activated must be delayed sufficiently to ensure the amplification of the data actually flowing from the memory cell to the bit line.
In a conventional one-transistor one-capacitor type semiconductor memory device, the activation timing of the sense amplifier is determined by an estimated delay time. The estimated delay time is determined by estimating the longest delay time among all of the word lines in a number of semiconductor memory devices, taking into account the variations occurring due to the manufacturing processes or the large wiring resistance. Therefore, the conventional semiconductor memory device has a disadvantage in that, even after the potential at the point on the word line farthest from the word decoder rises sufficiently to open the transfer gate transistor in the memory cell connected to that point, the sense amplifier is not activated until the estimated delay time has lapsed. If the estimated delay time is too long, the reading timing is also delayed too much.